HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 439

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

14.1.2
Figure 14.1 is a block diagram of the DMAC.
USBF
SIOF
Block Diagram
acknowledge)
X/Y memory
External I/O
External I/O
supporting
DACK0, DRAK0
(memory
mapped)
External
External
On-chip
module
ROM
RAM
(with
Selector
A/D converter
CHRAR
DREQ0
SCIF
DEIn
CMT
Ch0 to Ch3
Figure 14.1 DMAC Block Diagram
Bus state
controller
Section 14 Direct Memory Access Controller (DMAC)
Legend:
DMAOR:
SARn:
DARn:
DMATCRn:
CHCRn:
CHRAR:
DEIn:
n:
Bus interface
Interation
Register
Request
Start-up
Rev.6.00 Mar. 27, 2009 Page 381 of 1036
control
control
control
priority
control
DMAC operation register
DMAC source address register
DMAC destination address register
DMAC transfer count register
DMAC channel control register
DMA channel assign register
DMA transfer-end interrupt request to
CPU
0 to 3
DMAC module
DMATCRn
DMAOR
CHCRn
SARn
DARn
REJ09B0254-0600