HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 447

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 17—Acknowledge Mode (AM): AM specifies whether DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, DACK is always output regardless of this bit specification.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 17: AM
0
1
Bit 16—Acknowledge Level (AL): AL specifies the DACK (acknowledge) signal output is high
active or low active.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 16: AL
0
1
Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): DM1 and DM0 select
whether the DMA destination address is incremented, decremented, or fixed.
Bit 15: DM1
0
1
Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory.
Bit 14: DM0
0
1
0
1
Description
DACK output in read cycle
DACK output in write cycle
Description
Low-active output of DACK
High-active output of DACK
Fixed destination address*
Destination address is incremented (+1 in 8-bit transfer, +2 in
16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer)
Destination address is decremented (–1 in 8-bit transfer, –2 in
16-bit transfer, –4 in 32-bit transfer; illegal setting in 16-byte
transfer)
Reserved (illegal setting)
Description
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 389 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)