HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 494

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Section 14 Direct Memory Access Controller (DMAC)
CMCNT0 Count Timing
One of four peripheral clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) which are divided from the clock (Pφ)
can be selected with the CKS1 and CKS0 bits in CMCSR0. Figure 14.28 shows the timing.
Peripheral clock
(Pφ)
CMT clock
CMCNT0 input
clock
CMCNT0
N+1
N-1
N
Figure 14.28 Count Timing
14.4.4
Compare-Match
Compare-Match Flag Set Timing
When the CMCOR0 register and the CMCNT0 counter match, a compare-match signal is
generated and the CMF bit in the CMCSR0 register is set to 1. The compare-match signal is
generated upon the final state of the match (timing at which the CMCNT0 counter value is
updated). Consequently, after the CMCOR0 register and the CMCNT0 counter match, a compare-
match signal will not be generated until a CMCNT0 counter input clock occurs. Figure 14.29
shows a timing of the CMF bit setting.
Rev.6.00 Mar. 27, 2009 Page 436 of 1036
REJ09B0254-0600

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