HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 803
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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24.2.16 HcFmNumber
HcFmNumberb Register (H'040004BC)
The HcFmNumber register is a 16-bit counter. It indicates the reference of timing between events
occurring in the host controller and host controller driver. The host controller driver uses a 16-bit
value specified in this register and generates a 32-bit frame number without necessity for a
frequent access to the register.
Register: HcFmNumber
Bits
31–16
15–0
Reset
0h
0b
R/W
—
R
Offset: 3C–3F
Description
Reserved.
FrameNumber (FN)
These bits are incremented when HcFmRemaining is reloaded.
The count will return to H'0 after H'FFFF. When the host
controller transits to the UsbOperational state, these bits are
automatically incremented. After the host controller increments
the FramNumber bit and sends SOF in each frame boundary,
the content is written to HCCA before the host controller reads
first ED in the frame. After writing to HCCA, the host controller
sets the StartofFrame bit in the HcInterruptStatus register.
Rev.6.00 Mar. 27, 2009 Page 745 of 1036
Section 24 USB HOST Module
REJ09B0254-0600
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