HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 91

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table 2.2
Fields
MD
RB
BL
RC [11:0]
DSP
DMX
DMY
Q
M
I [3:0]
RF [1:0]
S
T
(S) STC:
(L) LDC:
OK:
Illegal instruction: Treated as illegal instruction, exception should be occurred
NG:
Third one is single-data transfer instruction, “MOVS.W” and “MOVS.L”. This instruction
accesses any memory location through LDB (figure 2.8). All DSP registers connect to the LDB
and be able to be source and destination register of the data transfer. It has word and longword
access modes. In the word mode, registers to be loaded or stored by this instruction are upper 16
bits (bits 31 to 16) for the DSP registers except A0G and A1G. When data is loaded into a register
Supervisor
Mode
MD = 1 &
DSP = 0
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
Detail Behavior Under Each SH3-DSP Mode
Keep previous value, nothing changed
Store SR to Rn, SR → Rn
Load Rn to SR, Rn → SR
Allowed to STC/LSC operation
User Mode
MD = 0 &
DSP = 0
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
S, L: illegal
instruction
DSP
Supervisor
Mode
MD = 1 &
DSP = 1
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: OK
DSP User
Mode
MD = 0 &
DSP = 1
S: OK,
L: NG
S: OK,
L: NG
S: OK,
L: NG
S: OK,
L: OK
S: OK,
L: NG
S: OK,
L: OK
S: OK,
L: OK
S: OK,
L: NG
S: OK,
L: NG
S: OK,
L: NG
S: OK,
L: OK
S: OK,
L: NG
S: OK,
L: NG
Rev.6.00 Mar. 27, 2009 Page 33 of 1036
Access to
DSP Related
Bits by
Dedicated
Instruction
SETRC
instruction
SETRC
instruction
REJ09B0254-0600
Initial Value after
Reset
1
1
1
0b000000000000
0
0
0
X
X
1111
X
X
X
Section 2 CPU