HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 224

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 7 Interrupt Controller (INTC)
7.1.2
Figure 7.1 is a block diagram of the INTC.
Rev.6.00 Mar. 27, 2009 Page 166 of 1036
REJ09B0254-0600
IPRA to IPRG:
PINT0 to PINT15
Legend:
SCIF:
WDT:
TMU:
RTC:
REF:
IRQ0 to IRQ5
ICR:
SCI:
Block Diagram
IRL3 to IRL0
SR:
Timer unit
Realtime clock unit
Serial communication interface
Serial communication interface (with FIFO)
Watchdog timer
Refresh requests in the bus state controller
Interrupt control register
Registers A-E for setting the interrupt
proprity levels
Status register
DMAC
H-UDI
SIOF
SCIF
WDT
TMU
ADC
RTC
REF
NMI
SCI
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(refresh request)
16
4
6
Figure 7.1 INTC Block Diagram
control
ICR
Input
IPRA to IPRG
identifier
DMAC:
H-UDI:
USBH:
LCDC:
USBF:
Priority
SIOF:
ADC:
PCC:
AFE:
IPR
Direct memory access controller
Analog-to-digital converter
Hitachi user-debugging interface
PCMCIA controller
LCD controller
USB host
USB function controller
AFE interface
Serial IO
interface
Bus
parator
Com-
INTC
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
3
Interrupt
request
2 1 0
SR
CPU
PCC
LCDC
USBH
USBF
AFE