HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 757

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 23 USB Function Controller
23.5.10 USBFIFO Clear Register (USBFCLR)
USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
Bit:
7
6
5
4
3
2
1
0
—
EP3
EP1
EP2
—
—
EP0o
EP0i
CLR
CLR
CLR
CLR
CLR
R/W:
W
W
W
W
W
W
W
W
Bit 7—Reserved
Bit 6—EP3 Clear (EP3 CLR): When 1 is written to this bit, the endpoint 3 transmit FIFO buffer
is initialized.
Bit 5—EP1 Clear (EP1 CLR): When 1 is written to this bit, both FIFOs in the endpoint 1 receive
FIFO buffer are initialized.
Bit 4—EP2 Clear (EP2 CLR): When 1 is written to this bit, both FIFOs in the endpoint 2
transmit FIFO buffer are initialized.
Bits 3 and 2—Reserved
Bit 1—EP0o Clear (EP0o CLR): When 1 is written to this bit, the endpoint 0 receive FIFO
buffer is initialized.
Bit 0—EP0i Clear (EP0i CLR): When 1 is written to this bit, the endpoint 0 transmit FIFO
buffer is initialized.
23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O)
USBEPSZ0O indicates, in bytes, the amount of data received from the host by endpoint 0.
Rev.6.00 Mar. 27, 2009 Page 699 of 1036
REJ09B0254-0600