HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 347

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

H'A0000000
H'C0000000
H'E0000000
Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is
H'00000000
H'20000000
H'40000000
H'60000000
H'80000000
Figure 12.2 Corresponding to Logical Address Space and Physical Address Space
on, it can optionally generate a physical address for the logical address. It can be
applied when the MMU is off and when the MMU is on and each physical address for
the logical address is equal except for upper three bits. When translating logical
addresses to arbitrary physical addresses, refer to table 12.3 "Physical Address Space
Map".
Logical address space
P0, U0
P1
P2
P3
P4
Rev.6.00 Mar. 27, 2009 Page 289 of 1036
Section 12 Bus State Controller (BSC)
Physical address space
Reserved area
Area 0 (CS0)
Area 2 (CS2)
Area 3 (CS3)
Area 4 (CS4)
Area 5 (CS5)
Area 6 (CS6)
Internal I/O
REJ09B0254-0600
H'00000000
H'04000000
H'08000000
H'0C000000
H'10000000
H'14000000
H'18000000