HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 346

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 12 Bus State Controller (BSC)
Table 12.2 Register Configuration
Name
Bus control register 1
Bus control register 2
Wait state control register 1
Wait state control register 2
Individual memory control
register
PCMCIA control register
Refresh timer control/status
register
Refresh timer counter
Refresh time constant register
Refresh count register
Synchronous DRAM
mode register
Notes: For details, see section 12.2.7, Synchronous DRAM Mode Register (SDMR).
12.1.5
Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32-
bit address spaces. The logical space is divided into five areas by the value of the upper bits of the
address. The physical space is divided into eight areas.
Logical space can be allocated at physical spaces using a memory management unit (MMU). For
details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for
physical spaces.
As listed in table 12.3, this LSI can be connected directly to six areas of memory/PC card
interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them.
CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA
interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the
corresponding bytes accessed.
Rev.6.00 Mar. 27, 2009 Page 288 of 1036
REJ09B0254-0600
* Initialized by power-on resets.
Area Overview
For
area 2
For
area 3
Abbr.
BCR1
BCR2
WCR1
WCR2
MCR
PCR
RTCSR
RTCNT
RTCOR
RFCR
SDMR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Initial Value* Address
H'0000
H'3FF0
H'3FF3
H'FFFF
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
—
H'FFFFFF60
H'FFFFFF62
H'FFFFFF64
H'FFFFFF66
H'FFFFFF68
H'FFFFFF6C
H'FFFFFF6E
H'FFFFFF70
H'FFFFFF72
H'FFFFFF74
H'FFFFD000–
H'FFFFDFFF
H'FFFFE000–
H'FFFFEFFF
Bus Width
16
16
16
16
16
16
16
16
16
16
8