HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 429

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

13.1.5
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bits 15 to 8 and 5 to 0 —Not referenced
Bits 7 and 6— Area 3 Idle Setting between Cycles (A3IW1, A3IW0): Specifies the number of
idle state cycles to insert between bus cycles when switching from a read address in area 3 of the
physical space to a write address in another space or within the same space.
Bit 7: A3IW1
0
1
Initial value:
Initial value:
Wait State Control Register 1 (WCR1)
R/W:
R/W:
Bit:
Bit:
Bit 6: A3IW0
0
1
0
1
A3IW1
WAIT
R/W
R/W
SEL
15
0
7
1
A3IW0
R/W
14
—
R
0
6
1
Description
1 idle state cycle inserted
1 idle state cycle inserted
2 idle state cycle inserted
3 idle state cycle inserted
A6IW1
A2IW1
R/W
R/W
13
1
5
1
A6IW0
A2IW0
R/W
R/W
12
1
4
1
Rev.6.00 Mar. 27, 2009 Page 371 of 1036
Section 13 Li Bus State Controller (LBSC)
A5IW1
R/W
11
—
R
1
3
0
A5IW0
R/W
10
—
R
1
2
0
REJ09B0254-0600
A4IW1
A0IW1
R/W
R/W
9
1
1
1
(Initial value)
A4IW0
A0IW0
R/W
R/W
8
1
0
1