HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 794

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 24 USB HOST Module
Register: HcInterruptStatus
Bits
4
3
2
1
0
Rev.6.00 Mar. 27, 2009 Page 736 of 1036
REJ09B0254-0600
Reset
0b
0b
0b
0b
0b
R/W
R/W
R/W
R/W
R/W
R/W
Offset: 0C–0F
Description
UnrecoverableError (UE)
This bit is set when the host controller detects a system error
that is not related to USB. HCD clears this bit after the host
controler is reset.
0: System error has not generated yet. (initial value)
1: System error is detected.
ResumeDetected (RD)
This bit is set when the host controller detects that a device of
USB issues a resume signal. This bit is not set when HCD sets
UsbResume state.
0: The resume signal is not detected. (initial value)
1: The resume signal is detected.
StartofFrame (SF)
This bit is set by the host controller when each frame starts and
after the HccaFrameNumber is updated. The host controller
simultaneously generates the SOF token.
0: Each frame has not initiated or HccaFrame Number is not
1: Initiation of each frame and updating of HccaFrameNumber
WritebackDoneHead (WDH)
This bit is set immediately after the host controller has written
HcDoneHead to HccaDoneHead. HccaDoneHead is not
updated until this bit is cleared. HCD should clear this bit only
after the content of HccaDoneHead has been stored.
0: When cleared after set to 1. (initial value)
1: When HcDoneHead is written to HccaDonehead.
SchedulingOverrun (SO)
This bit is set when the USB schedule has overrun after
HccaFrameNumber has updated. SchedulingOverrun also
increments the SchedulingOverrunCount bit in
HcCommandStatus.
0: The USB schedule has not overrun. (initial value)
1: The USB schedule has overrun.
updated (initial value)