HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 358

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 12 Bus State Controller (BSC)
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states
inserted into physical space area 6. Also specify the burst pitch for burst transfer.
A6W2
0
1
Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states
inserted into physical space area 5. Also specify the burst pitch for burst transfer.
Bit 12:
A5W2
0
1
Rev.6.00 Mar. 27, 2009 Page 300 of 1036
REJ09B0254-0600
Bit 15:
Bit 14:
A6W1
0
1
0
1
Bit 11:
A5W1
0
1
0
1
Bit 13:
A6W0
0
1
0
1
0
1
0
1
Bit 10:
A5W0
0
1
0
1
0
1
0
1
Inserted
Wait States
0
1
2
3
4
6
8
10
(Initial value)
Inserted
Wait States
0
1
2
3
4
6
8
10
(Initial value)
First Cycle
First Cycle
WAIT Pin
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
WAIT Pin
Disable
Enable
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Enable
Description
Description
Number of States
Per Data Transfer WAIT Pin
2
2
3
4
4
6
8
10
Number of States
Per Data Transfer WAIT Pin
2
2
3
4
4
6
8
10
(Excluding First Cycle)
(Excluding First Cycle)
Burst Cycle
Burst Cycle
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable