HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 841

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

25.2.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the timing of the generation of the vertical (scan direction and vertical
direction) sync signals (FLM/Vsync) for the LCD module.
Bit 11—Reserved
Bits 15 to 12—Vertical Sync Signal Width (VSYNW): Set the width of the vertical sync signals
(FLM and Vsync) (unit: line).
Subtract 2 from the setting (0 to 15 (H'F)).
Example: For a vertical sync signal width of 1 line
Bits 10 to 0— Vertical Sync Signal Output Position (VSYNP): Set the output position of the
vertical sync signals (FLM and Vsync) (unit: line).
Subtract 2 from the setting (0 to 2046 (H'7FE)).
DSTN should be set to an odd number value. It is handled as (setting value + 1)/ 2.
Example: For an 480-line LCD module and a vertical retrace period of 0 lines (in other words,
Initial value:
R/W:
Bit:
VSYN
VSYNW = (1 – 1) = 0 = H'0
VTLN = 479 and the vertical sync signal is active for the first line):
• Single display
• Dual displays
R/W
W3
15
0
VSYNP=[(1-1)+VTLN] mod (VTLN+1) = [(1-1)+479] mod (479+1)
VSYNP=[(1-1)×2+VTLN] mod (VTLN+1) = [(1-1)×2+479] mod (479+1)
VSYN
R/W
W2
14
0
VSYN
R/W
W1
13
0
VSYN
R/W
W0
12
0
11
—
R
0
VSYNP
R/W
10
10
0
VSYNP
R/W
9
9
0
VSYNP
R/W
8
8
1
VSYNP
= 479 mod 480 = 479
= H'1DF
R/W
Rev.6.00 Mar. 27, 2009 Page 783 of 1036
7
7
1
= 479 mod 480 = 479
= H'1DF
VSYNP
R/W
6
6
1
VSYNP
R/W
5
5
0
VSYNP
Section 25 LCD Controller
R/W
4
4
1
VSYNP
R/W
3
3
1
REJ09B0254-0600
VSYNP
R/W
2
2
1
VSYNP
R/W
1
1
1
VSYNP
R/W
0
0
1