HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 192

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 4 Exception Handling
Exception
Type
General
interrupt
requests
Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.
4.2.3
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. When a power-on reset and a manual reset occur simultaneously, the
power-on reset has priority.
All general exception events occur in a relative order in the execution sequence of an instruction
(i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (general illegal instruction exception, unconditional trap exception,
and illegal slot instruction exception) are detected in the decode stage (ID stage) of different
instructions and are mutually exclusive events in the instruction pipeline. They have the same
execution priority. Figure 4.2 shows the order of general exception acceptance.
Rev.6.00 Mar. 27, 2009 Page 134 of 1036
REJ09B0254-0600
2. The user defines the break point traps. 1 is a break point before instruction execution
3. Use software to specify relative priorities of external hardware interrupts and peripheral
4. See section 4.5.2, General Exceptions for details.
Acceptance of Exceptions
and 11 is a break point after instruction execution. For an operand break point, use 11.
module interrupts (see section 7, Interrupt Controller (INTC)).
Current
Instruction
Completed
Exception Event
Nonmaskable interrupt 3
External hardware
interrupt
H-UDI interrupt
Priority *
4 *
4 *
3
3
1
Exception
Order
—
—
—
—
Vector
Address
—
—
H'00000600
Vector Offset
H'00000600
H'00000600