HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 130

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 2 CPU
Instruction
DMULU.L Rm,Rn
DT
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.L
MAC.W
MUL.L
MULS.W Rm,Rn
MULU.W Rm,Rn
NEG
NEGC
SUB
SUBC
SUBV
Rev.6.00 Mar. 27, 2009 Page 72 of 1036
REJ09B0254-0600
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
@Rm+,@Rn+
@Rm+,@Rn+
Rm,Rn
Operation
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Rn – 1 → Rn, if Rn =
0, 1 → T, else 0 → T
A byte in Rm is sign-
extended → Rn
A word in Rm is sign-
extended → Rn
A byte in Rm is zero-
extended → Rn
A word in Rm is zero-
extended → Rn
Signed operation of (Rn)
× (Rm) + MAC → MAC,
Rn + 4 → Rn,
Rm + 4 → Rm,
32 × 32 + 64 → 64 bits
Signed operation of (Rn)
× (Rm) + MAC → MAC,
Rn + 2 → Rn,
Rm + 2 → Rm,
16 × 16 + 64 → 64 bits
Rn × Rm → MACL,
32 × 32 → 32 bits
Signed operation of Rn
× Rm → MACL,
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MACL,
16 × 16 → 32 bits
0–Rm → Rn
0–Rm–T → Rn,
Borrow → T
Rn–Rm → Rn
Rn–Rm–T → Rn,
Borrow → T
Rn–Rm → Rn,
Underflow → T
Code
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Privileged
Mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cycles T Bit
2
(to 5) *
1
1
1
1
1
2
(to 5) *
2
(to 5) *
2
(to 5) *
1
(to 3) *
1
(to 3) *
1
1
1
1
1
1
1
1
1
2
2
—
Comparison
result
—
—
—
—
—
—
—
—
—
—
Borrow
—
Borrow
Underflow