HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 597

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

17.5
Note the following points when using the SCI.
SCTDR Write and TDRE Flags: The TDRE bit in the serial status register (SCSSR) is a status
flag indicating loading of transmit data from the SCTDR into the SCTSR. The SCI sets TDRE to 1
when it transfers data from the SCTDR to the SCTSR. Data can be written to the SCTDR
regardless of the TDRE bit state. If new data is written in the SCTDR when TDRE is 0, however,
the old data stored in the SCTDR will be lost because the data has not yet been transferred to the
SCTSR. Before writing transmit data to the SCTDR, be sure to check that TDRE is set to 1.
Simultaneous Multiple Receive Errors: Table 17.14 indicates the state of the SCSSR status
flags when multiple receive errors occur simultaneously. When an overrun error occurs, the
SCRSR contents cannot be transferred to the SCRDR, so receive data is lost.
Table 17.14 SCSSR Status Flags and Transfer of Receive Data
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error 1
X: Receive data is not transferred from SCRSR to SCRDR.
O: Receive data is transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD0 pin directly
when a framing error (FER) is detected. In the break state, the input from the RxD0 pin consists of
all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI
receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: The TxD0 pin I/O condition and level can be determined by means of
the SCP0DT bit of the port SC data register (SCPDR) and bits SCP0MD0 and SCP0MD1 of the
port SC control register (SCPCR). These bits can be used to send breaks. To send a break during
serial transmission, clear the SCP0DT bit to 0 (designating low level), then clear the TE bit to 0
(halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of
the current transmission state, and 0 is output from the TxD0 pin.
Usage Notes
1
0
1
1
RDRF
0
0
SCSSR Status Flags
Section 17 Serial Communication Interface (SCI)
ORER
1
0
0
1
1
0
1
Rev.6.00 Mar. 27, 2009 Page 539 of 1036
FER PER
0
1
0
1
0
1
1
0
0
1
0
1
1
1
Receive Data Transfer
SCRSR → SCRDR
X
O
O
X
X
O
X
REJ09B0254-0600