HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 460

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Section 14 Direct Memory Access Controller (DMAC)
In order to output a transfer request from an on-chip supporting module, set the corresponding
interrupt enable bit for outputting the interrupt signal.
When the interrupt request signal from an on-chip supporting module is used as a DMA transfer
request signal, an interrupt is not generated to the CPU.
The DMA transfer request signals shown in table 14.4 are automatically canceled when the
corresponding DMA transfer is completed. This operation is provided at the first transfer in cycle
steal mode, and at the last transfer in burst mode.
14.3.3
Channel Priority
When the DMAC receives multiple transfer requests simultaneously, it provides transfer operation
according to a specified priority order. The fixed mode or round-robin mode can be selected for
the channel priority with the PR1 and PR0 bit in the DMA operation register (DMAOR).
Fixed Mode: The channel priority is fixed. There are three kinds of orders as follows:
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
The priority is selected by the PR1 and PR0 bits in the DMA operation register (DMAOR).
Round-Robin Mode: The priority order is rotated each time one transfer unit (word, byte, or
longword) of data has been transferred. The channel on which the transfer was just finished is
located at the lowest in priority. The round-robin mode operation is shown in figure 14.3. The
priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after a reset.
Rev.6.00 Mar. 27, 2009 Page 402 of 1036
REJ09B0254-0600

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