NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 98

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.1.2.1
5.1.2.2
5.1.2.3
5.1.2.4
5.1.2.5
5.1.2.6
5.1.2.7
98
I/O Reads and Writes
Configuration Reads and Writes
Target / Master Aborts
Dual Address Cycle (DAC)
Memory Reads and Writes
The bridge bursts memory writes on PCI that are received as a single packet from DMI. The bridge
will perform write combining if BPC.WCE (D30:F0:Offset 4Ch:bit 31) is set.
The bridge generates single DW I/O read and write cycles. When the cycle completes on PCI bus,
the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in
the downbound queue and may be passed by a postable cycle.
The bridge generates single DW configuration read and write cycles. When the cycle completes on
PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in
the downbound queue and may be passed by a postable cycle.
Locked Cycles
The bridge propagates locks from DMI per the PCI specification. The PCI bridge implements bus
lock, which means the arbiter will not grant to any agent except DMI while locked.
If a locked read results in a target or master abort, the lock is not established (as per the PCI
specification). Agents north of the ICH6 must not forward a subsequent locked read to the bridge if
they see the first one finish with a failed completion.
When a cycle initiated by the bridge is master/target aborted, the bridge will not re-attempt the
same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW
of the transaction. For all non-postable cycles, a target abort response packet is returned for each
DW that was master or target aborted on PCI. The bridge drops posted writes that abort.
Secondary Master Latency Timer
The bridge implements a Master Latency Timer via the SLT register which, upon expiration, causes
the de-assertion of FRAME# at the next legal clock edge when there is another active request to
use the PCI bus.
The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above
4 GB.
Intel
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I/O Controller Hub 6 (ICH6) Family Datasheet