NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 679

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

19.1.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PCICMD—PCI Command Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-Plug and power
management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power
1 = Internal INTx# messages will not be generated.
This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx
and de-assert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is
set.
Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification .
SERR# Enable (SEE) — R/W.
0 = Disable.
1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.
Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification .
Parity Error Response (PER) — R/W.
0 = Disable.
1 = Indicates that the device is capable of reporting parity errors as a master on the backbone.
VGA Palette Snoop (VPS) — Reserved per the PCI Express* Base Specification .
Postable Memory Write Enable (PMWE) — Reserved per the PCI Express* Base Specification .
Special Cycle Enable (SCE) — Reserved per the PCI Express* Base Specification .
Bus Master Enable (BME) — R/W.
0 = Disable. All cycles from the device are master aborted
1 = Enable. Allows the root port to forward cycles onto the backbone from a PCI Express* device.
Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit registers are
1 = Enable. Allows memory cycles within the range specified by the memory base and limit
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be
management and MSI is not enabled.
master aborted on the backbone.
registers can be forwarded to the PCI Express device.
aborted on the backbone.
forwarded to the PCI Express device.
04–05h
0000h
Description
Attribute:
Size:
PCI Express* Configuration Registers
R/W, RO
16 bits
679