NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 560

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.2.3
14.2.3.1
560
Table 14-4. Debug Port Register Address Map
USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base Address
Register (MEM_BASE), as the standard EHCI registers. The base offset for the debug port
registers (A0h) is declared in the Debug Port Base Offset Capability Register at Configuration
offset 5Ah (D29:F7:offset 5Ah). The specific EHCI port that supports this debug capability (port 0)
is indicated by a 4-bit field (bits 20
address map of the Debug Port registers is shown in
NOTES:
CNTL_STS—Control/Status Register
Offset:
Default Value:
1. All of these registers are implemented in the core well and reset by PLTRST#, EHC HCRESET, and a EHC
2. The hardware associated with this register provides no checks to ensure that software programs the interface
MEM_BASE +
27:17
D3-to-D0 transition
correctly. How the hardware behaves when programmed illegally is undefined.
Bit
31
30
29
28
16
AC–AFh
A8–ABh
A0–A3h
A4–A7h
B0–B3h
Offset
Reserved
OWNER_CNT — R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately taken away from
Reserved
ENABLED_CNT — R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the same conditions
1 = Debug port is enabled for operation. Software can directly set this bit if the port is already
Reserved
DONE_STS — R/WC. Software can clear this by writing a 1 to it.
0 = Request Not complete
1 = Set by hardware to indicate that the request is complete.
the companion Classic USB Host controller) If the port was already owned by the EHCI
controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits
in the standard EHCI registers.
where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default)
enabled in the associated PORTSC register (this is enforced by the hardware).
DATABUF[3:0]
DATABUF[7:4]
.
MEM_BASE + A0h
00000000h
CNTL_STS
Mnemonic
CONFIG
USBPID
Control/Status
USB PIDs
Data Buffer (Bytes 3:0)
Data Buffer (Bytes 7:4)
Configuration
–
23) in the HCSPARAMS register of the EHCI controller. The
Intel
Register Name
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Table
14-4.
R/W, R/WC, RO, WO
32 bits
00007F01h
00000000h
00000000h
00000000h
00000000h
Default
R/W, R/WC,
R/W, RO
RO, WO
Type
R/W
R/W
R/W