NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 106

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.3.1
5.3.1.1
106
LAN Controller PCI Bus Interface
As a Fast Ethernet controller, the role of the ICH6 integrated LAN controller is to access
transmitted data or deposit received data. The LAN controller, as a bus master device, initiates
memory cycles via the PCI bus to fetch or deposit the required data.
To perform these actions, the LAN controller is controlled and examined by the processor via its
control and status structures and registers. Some of these control and status structures reside in the
LAN controller and some reside in system memory. For access to the LAN controller’s Control/
Status Registers (CSR), the LAN controller acts as a slave (in other words, a target device). The
LAN controller serves as a slave also while the processor accesses the EEPROM.
Bus Slave Operation
The ICH6 integrated LAN controller serves as a target device in one of the following cases:
The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The
LAN controller treats accesses to these memory spaces differently.
Control/Status Register (CSR) Accesses
The integrated LAN controller supports zero wait-state single cycle memory or I/O mapped
accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space
to accomplish this. Based on its needs, the software driver uses either memory or I/O mapping to
access these registers. The LAN controller provides four valid KB of CSR space that include the
following elements:
In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN
controller is the target.
Retry Premature Accesses
The LAN controller responds with a Retry to any configuration cycle accessing the LAN controller
before the completion of the automatic read of the EEPROM. The LAN controller may continue to
Retry any configuration accesses until the EEPROM read is complete. The LAN controller does
not enforce the rule that the retried master must attempt to access the same address again in order to
complete any delayed transaction. Any master access to the LAN controller after the completion of
the EEPROM read is honored.
•
•
•
•
•
•
•
•
•
Processor accesses to the LAN controller System Control Block (SCB) Control/Status
Registers (CSR)
Processor accesses to the EEPROM through its CSR
Processor accesses to the LAN controller PORT address via the CSR
Processor accesses to the MDI control register in the CSR
System Control Block (SCB) registers
PORT register
EEPROM control register
MDI control register
Flow control registers
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet