NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 332

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI-to-PCI Bridge Registers (D30:F0)
9.1.12
332
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
SECSTS—Secondary Status Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
effect.
10:9
Bit
4:0
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = Parity error not detected.
1 = Intel
Received System Error (R SE) — R/WC.
0 = SERR# assertion not received
1 = SERR# assertion is received on PCI.
Received Master Abort (RMA) — R/WC.
0 = No master abort.
1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the cycle is
Received Target Abort (RTA) — R/WC.
0 = No target abort.
1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is target-aborted
Signaled Target Abort (STA) — R/WC.
0 = No target abort.
1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a target abort.
DEVSEL# Timing (DEVT) — RO.
01h = Medium decode timing.
Data Parity Error Detected (DPD) — R/WC.
0 = Conditions described below not met.
1 = The ICH6 sets this bit when all of the following three conditions are met:
Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI target logic
is capable of receiving fast back-to-back cycles.
Reserved
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable only.
Reserved
• The bridge is the initiator on PCI.
• PERR# is detected asserted or a parity error is detected internally
• BCTRL.PERE (D30:F0:3E bit 0) is set.
master-aborted. For (G)MCH/ICH6 interface packets that have completion required, this must
also cause a target abort to be returned and sets PSTS.STA. (D30:F0:06 bit 11)
on PCI. For (G)MCH/ICH6 interface packets that have completion required, this event must
also cause a target abort to be returned, and sets PSTS.STA. (D30:F0:06 bit 11).
®
ICH6 PCI bridge detected an address or data parity error on the PCI bus
1E
0280h
–
1Fh
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
16 bits
R/WC, RO