NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 511
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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13.1.10
13.1.11
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
HEADTYP—Header Type Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
For functions 1, 2, and 3, this register is hardwired to 00h. For function 0, bit 7 is determined by the
values in the USB Function Disable bits (11:8 of the Function Disable register Chipset
Configuration Registers:Offset 3418h).
BASE—Base Address Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
31:16
15:5
Bit
4:1
Bit
6:0
0
7
Reserved
Base Address — R/W. Bits [15:5] correspond to I/O address signals AD [15:5], respectively. This
gives 32 bytes of relocatable I/O space.
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate that the base address field in this
register maps to I/O space.
Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
Since the upper functions in this device can be individually hidden, this bit is based on the function-
disable bits in Chipset Configuration Space:Offset 3418h as follows:
Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout.
D29:F7_Disable
(bit 15)
0b
X
X
X
1
0Eh
FN 0: 80h
FN 1: 00h
FN 2: 00h
FN 3: 00h
20
00000001h
–
D29:F3_Disable
23h
(bit 11)
0b
X
X
X
1
D29:F2_Disable
Description
Description
(bit10)
0b
X
X
X
Attribute:
Size:
1
Attribute:
Size:
D29:F1_Disable
UHCI Controllers Registers
(bit 9)
0b
X
X
X
1
RO
8 bits
R/W, RO
32 bits
Device (this bit)
Multi-Function
1
1
1
1
0
511
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