NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 576

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
15.2.12
.
15.2.13
576
Note: This register is in the resume well and is reset by RSMRST#.
AUX_CTL—Auxiliary Control Register (SMBus—D31:F3)
Register Offset:
Default Value:
Lockable:
SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBus—D31:F3)
Register Offset:
Default Value:
This register is only applicable in the TCO compatible mode.
Bit
7:2
Bit
7:3
1
0
2
1
0
Reserved
Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable.
1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to
Automatically Append CRC (AAC) — R/W.
0 = ICH6 will Not automatically append the CRC.
1 = The ICH6 will automatically append the CRC. This bit must not be changed during SMBus
Reserved
SMLINK_CLK_CTL — R/W.
0 = ICH6 will drive the SMLINK0 pin low, independent of what the other SMLINK logic would
1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state of the pin.
SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLINK1 pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLINK0 pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
a single register. This enables the block commands to transfer or receive up to 32-bytes before
the ICH6 generates an interrupt.
transactions or undetermined behavior will result. It should be programmed only once during the
lifetime of the function.
otherwise indicate for the SMLINK0 pin.
(Default)
SMBASE + 0Dh
00h
No
SMBASE + 0Eh
See below
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
Attribute:
Size:
R/W
8 bits
Resume
R/W, RO
8 bits