NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 264

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.41
264
D31IP—Device 31 Interrupt Pin Register
Offset Address:
Default Value:
31:16
15:12
11:8
Bit
7:4
3:0
Reserved
SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
PATA Pin (SMIP) — R/W. This field indicates which pin the PATA controller drives as its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
PCI Bridge Pin (PIP) — RO. Currently, the PCI bridge does not generate an interrupt, so this field
is read-only and 0.
3100–3103h
00042210h
Intel
®
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
32-bit
R/W, RO