NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 597

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

16.2.2
16.2.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
x_CIV—Current Index Value Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 04h.
NOTE: Reads across DWord boundaries are not supported.
x_LVI—Last Valid Index Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 05h.
NOTE: Reads across DWord boundaries are not supported.
Bit
7:5
4:0
Bit
7:5
4:0
Hardwired to 0
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within the list of 32
descriptors is currently being processed. As each descriptor is processed, this value is incremented.
The value rolls over after it reaches 31.
Hardwired to 0.
Last Valid Index [4:0] — R/W. This value represents the last valid descriptor in the list. This value is
updated by the software each time it prepares a new buffer and adds it to the list.
NABMBAR + 04h (PICIV),
NABMBAR + 14h (POCIV),
NABMBAR + 24h (MCCIV)
MBBAR + 44h (MC2CIV)
MBBAR + 54h (PI2CIV)
MBBAR + 64h (SPCIV)
00h
No
NABMBAR + 05h (PILVI),
NABMBAR + 15h (POLVI),
NABMBAR + 25h (MCLVI)
MBBAR + 45h (MC2LVI)
MBBAR + 55h (PI2LVI)
MBBAR + 65h (SPLVI)
00h
No
AC ’97 Audio Controller Registers (D30:F2)
Description
Description
Attribute:
Size:
Power Well:
Size:
Power Well:
Attribute:
RO
8 bits
Core
R/W
8 bits
Core
597