NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 379

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.4.11
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating
point error interrupt, IRQ13, cannot be programmed for level mode.
Bit
7
6
5
4
3
2
1
0
IRQ15 ECL — R/W.
0 = Edge
1 = Level
IRQ14 ECL — R/W.
0 = Edge
1 = Level
Reserved. Must be 0.
IRQ12 ECL — R/W.
0 = Edge
1 = Level
IRQ11 ECL — R/W.
0 = Edge
1 = Level
IRQ10 ECL — R/W.
0 = Edge
1 = Level
IRQ9 ECL — R/W.
0 = Edge
1 = Level
Reserved. Must be 0.
4D1h
00h
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
R/W
8 bits
379