NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 686

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
19.1.17
19.1.18
19.1.19
19.1.20
686
PMLU32—Prefetchable Memory Limit Upper 32 Bits
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
CAPP—Capabilities List Pointer Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
INTR—Interrupt Information Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
31:0
31:0
15:8
Bit
Bit
Bit
7:0
Bit
7:0
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the prefetchable
address base.
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the prefetchable
address limit.
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first entry in the
capabilities list is at 40h in configuration space.
Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the root port. At reset, this
register takes on the following values, which reflect the reset state of the D28IP register in chipset
configuration space:
NOTE: The value that is programmed into D28IP is always reflected in this register.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Port
1
2
3
4
28–2Bh
00000000h
2C–2Fh
00000000h
34h
40h
3C–3Dh
See bit description
Reset Value
D28IP.P1IP
D28IP.P2IP
D28IP.P3IP
D28IP.P4IP
Intel
Description
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
32 bits
32 bits
R0
16 bits
R/W
R/W
8 bits
R/W, RO