NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 259

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

7.1.29
7.1.30
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
BCR—Backbone Configuration Register
Offset Address:
Default Value:
RPC—Root Port Configuration Register
Offset Address:
Default Value:
31:8
31:8
Bit
7:5
3:0
Bit
5:4
3:2
1:0
4
7
6
Reserved
Backbone Configuration Register Bits[8:5] — R/W. BIOS sets this field to 111b.
Reserved
Backbone Configuration Register Bits[3:0] — R/W. BIOS sets this field to 0101b.
Reserved
High Priority Port Enable (HPE) — R/W.
0 = The high priority path is not enabled.
1 = The port selected by the HPP field in this register is enabled for high priority. It will be
Reserved
High Priority Port (HPP) — R/W. This field controls which port is enabled for high priority when
the HPE bit in this register is set.
11 = Port 4
10 = Port 3
01 = Port 2
00 = Port 1
Reserved
Port Configuration (PC) — RO. This field controls how the PCI bridges are organized in various
modes of operation. For the following mappings, if a port is not shown, it is considered a x1 port
with no connection.
These bits represent the strap values of ACZ_SDOUT (bit 1) and ACZ_SYNC (bit 0) when TP[3]
is not pulled low at the rising edge of PWROK.
11 = 1 x4, Port 1 (x4) (Enterprise applications only)
10 = Reserved
01 = Reserved
00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1)
These bits live in the resume well and are only reset by RSMRST#.
arbitrated above all other VC0 (including integrated VC0) devices.
0220–0223h
000008000h
0224–0227h
0000000xh
Description
Description
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
R/W
32-bit
R/W, RO
32-bit
259