NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 674

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.2.41
18.2.42
674
®
High Definition Audio Controller Registers (D27:F0)
SDBDPU—Stream Descriptor Buffer Descriptor List Pointer
SDBDPL—Stream Descriptor Buffer Descriptor List Pointer
Lower Base Address Register
(Intel
Memory Address: Input Stream[0]: HDBAR + 98h
Default Value:
Upper Base Address Register (Intel
Controller
—D27:F0)
Memory Address: Input Stream[0]: HDBAR + 9Ch
Default Value:
31:7
31:0
Bit
6:0
Bit
®
Buffer Descriptor List Pointer Lower Base Address — R/W. Lower address of the Buffer
Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be
corrupted.
Hardwired to 0 forcing alignment on 128-B boundaries.
Buffer Descriptor List Pointer Upper Base Address — R/W. Upper 32-bit address of the Buffer
Descriptor List. This value should only be modified when the RUN bit is 0, or DMA transfer may be
corrupted.
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + B8h
Input Stream[2]: HDBAR + D8h
Input Stream[3]: HDBAR + F8h
Output Stream[0]: HDBAR + 118h
Output Stream[1]: HDBAR + 138h
Output Stream[2]: HDBAR + 158h
Output Stream[3]: HDBAR + 178h
00000000h
Input Stream[1]: HDBAR + BCh
Input Stream[2]: HDBAR + DCh
Input Stream[3]: HDBAR + FCh
Output Stream[0]: HDBAR + 11Ch
Output Stream[1]: HDBAR + 13Ch
Output Stream[2]: HDBAR + 15Ch
Output Stream[3]: HDBAR + 17Ch
00000000h
§
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
®
High Definition Audio
R/W,RO
R/W
32 bits
32 bits