NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 668

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
668
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High Definition Audio Controller Registers (D27:F0)
Bit
3
2
1
0
FIFO Error Interrupt Enable — R/W. This bit controls whether the occurrence of a FIFO error
(overrun for input or underrun for output) will cause an interrupt or not. If this bit is not set, bit 3in the
Status register will be set, but the interrupt will not occur. Either way, the samples will be dropped.
Interrupt on Completion Enable — R/W. This bit controls whether or not an interrupt occurs when
a buffer completes with the IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register
will be set, but the interrupt will not occur.
Stream Run (RUN) — R/W.
0 = When cleared to 0, the DMA engine associated with this input stream will be disabled. The
1 = When set to 1, the DMA engine associated with this input stream will be enabled to transfer
Stream Reset (SRST) — R/W.
0 = Writing a 0 causes the corresponding stream to exit reset. When the stream hardware is ready
1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor registers
hardware will report a 0 in this bit when the DMA engine is actually stopped. Software must
read a 0 from this bit before modifying related control registers or restarting the DMA engine.
data from the FIFO to the main memory. The SSYNC bit must also be cleared in order for the
DMA engine to run. For output streams, the cadence generator is reset whenever the RUN bit
is set.
to begin operation, it will report a 0 in this bit. Software must read a 0 from this bit before
accessing any of the stream registers.
(except the SRST bit itself) and FIFO’s for the corresponding stream are reset. After the stream
hardware has completed sequencing into the reset state, it will report a 1 in this bit. Software
must read a 1 from this bit to verify that the stream is in reset. The RUN bit must be cleared
before SRST is asserted.
Intel
Description
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I/O Controller Hub 6 (ICH6) Family Datasheet