NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 656
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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Intel
18.2.7
18.2.8
18.2.9
656
®
High Definition Audio Controller Registers (D27:F0)
WAKEEN—Wake Enable Register
(Intel
Memory Address: HDBAR + 0Ch
Default Value:
STATESTS—State Change Status Register
(Intel
Memory Address: HDBAR + 0Eh
Default Value:
GSTS—Global Status Register
(Intel
Memory Address: HDBAR + 10h
Default Value:
15:3
15:3
15:2
Bit
2:0
Bit
2:0
Bit
1
0
®
®
®
Reserved.
SDIN Wake Enable Flags — R/W. These bits control which SDI signal(s) may generate a wake
event. A 1b in the bit mask indicates that the associated SDIN signal is enabled to generate a wake.
Bit 0 is used for SDI[0]
Bit 1 is used for SDI[1]
Bit 2 is used for SDI[2]
NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not
Reserved.
SDIN State Change Status Flags — R/WC. Flag bits that indicate which SDI signal(s) received a
state change event. The bits are cleared by writing 1s to them.
Bit 0 = SDI[0]
Bit 1 = SDI[1]
Bit 2 = SDI[2]
NOTE: These bits are in the resume well and only cleared on a power on reset. Software must not
Reserved.
Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush cycle initiated when
the Flush Control bit (HDBAR + 08h, bit 1) was set has completed. Software must write a 1 to clear
this bit before the next time the Flush Control bit is set to clear the bit.
Reserved.
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
make assumptions about the reset state of these bits and must set them appropriately.
make assumptions about the reset state of these bits and must set them appropriately.
0000h
0000h
0000h
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
16 bits
16 bits
16 bits
R/W
R/WC
R/WC
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