NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 355

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.1.20
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
15:14
Bit
7:4
13
12
11
10
9
8
3
2
1
0
Reserved
CNF2_LPC_EN — R/W. Microcontroller Enable # 2.
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used
CNF1_LPC_EN — R/W. Super I/O Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used
MC_LPC_EN — R/W. Microcontroller Enable # 1.
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used
KBC_LPC_EN — R/W. Keyboard Enable.
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used
GAMEH_LPC_EN — R/W. High Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is
GAMEL_LPC_EN — R/W. Low Gameport Enable
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is
Reserved
FDD_LPC_EN — R/W. Floppy Drive Enable
0 = Disable.
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the
LPT_LPC_EN — R/W. Parallel Port Enable
0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the
COMB_LPC_EN — R/W. Com Port B Enable
0 = Disable.
1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the
COMA_LPC_EN — R/W. Com Port A Enable
0 = Disable.
1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the
for a microcontroller.
for Super I/O devices.
for a microcontroller.
for a microcontroller.
used for a gameport.
used for a gameport.
LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).
LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).
LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).
LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
82h
0000h
–
83h
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W
16 bit
Core
355