NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 131

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.9
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Intel
Table 5-12. Interrupt Controller Core Connections
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH6. In the following
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH6 incorporates the functionality of two 8259 interrupt controllers that provide system
interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard
controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,
this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the
compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0
shows how the cores are connected.
The ICH6 cascades the slave controller onto the master controller through master controller
interrupt input 2. This means there are only 15 possible interrupts for the ICH6 PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and
IRQ13.
descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface
of the 8259s, after the required inversions have occurred. Therefore, the term “high” indicates
“active,” which means “low” on an originating PIRQ#.
Master
Slave
8259
Input
8259
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Internal
Keyboard
Internal
Serial Port A
Serial Port B
Parallel Port / Generic
Floppy Disk
Parallel Port / Generic
Internal Real Time Clock
Generic
Generic
Generic
PS/2 Mouse
Internal
IDE cable, SATA
IDE cable, SATA
Typical Interrupt
Source
Internal Timer / Counter 0 output / HPET #0
IRQ1 via SERIRQ
Slave controller INTR output
IRQ3 via SERIRQ, PIRQ#
IRQ4 via SERIRQ, PIRQ#
IRQ5 via SERIRQ, PIRQ#
IRQ6 via SERIRQ, PIRQ#
IRQ7 via SERIRQ, PIRQ#
Internal RTC / HPET #1
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO interrupt
if FERR# not needed.
IDEIRQ (legacy mode, non-combined or combined
mapped as primary), SATA Primary (legacy mode), or via
SERIRQ or PIRQ#
IDEIRQ (legacy mode — combined, mapped as
secondary), SATA Secondary (legacy mode) or via
SERIRQ or PIRQ#
Connected Pin / Function
Functional Description
–
7.
Table 5-12
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