NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 158

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.14.5.3
5.14.5.4
5.14.6
5.14.6.1
158
Note: The 33 MHz clock to the ICH6 is “free-running” and is not affected by the STP_PCI# signal.
POPUP (Auto C3/C4 to C2) (Mobile Only)
To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be set. This will
cause the BM_STS bit to read as 0 even if some bus master activity is present. If this is not done,
then the software may avoid even attempting to go to the C3 or C4 state if it sees the BM_STS bit
as 1.
If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH6 will treat bus master activity as a
break event. When reaching the C2 state, if there is any bus master activity, the ICH6 will return
the processor to a C0 state.
When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH6 enables a mode of operation
where standard (non-isoch) bus master activity will not be treated as a full break event from the C3
or C4 states. Instead, these will be treated merely as bus master events and return the platform to a
C2 state, and thus allow snoops to be performed.
After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even if the
ARB_DIS bit is set.
POPDOWN (Auto C2 to C3/C4) (Mobile Only)
After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4) is set, the
platform can return to a C3 or C4 state (depending on where it was prior to going back up to C2).
This behaves similar to the Deferred C3/C4 transition, and will keep the processor in a C2 state
until:
Dynamic PCI Clock Control (Mobile Only)
The PCI clock can be dynamically controlled independent of any other low-power state. This
control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design
Guide, and is transparent to software.
The Dynamic PCI Clock control is handled using the following signals:
Conditions for Checking the PCI Clock
When there is a lack of PCI activity the ICH6 has the capability to stop the PCI clocks to conserve
power. “PCI activity” is defined as any activity that would require the PCI clock to be running.
Any of the following conditions will indicate that it is not okay to stop the PCI clock:
•
•
•
•
•
•
•
Bus masters are no longer active.
A break event occurs. Note that bus master traffic is not a break event in this case.
CLKRUN#:
STP_PCI#:
Cycles on PCI or LPC
Cycles of any internal device that would need to go on the PCI bus
SERIRQ activity
Used by PCI and LPC peripherals to request the system PCI clock to run
Used to stop the system PCI clock
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet