NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 694

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI Express* Configuration Registers
19.1.29
694
LSTS—Link Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
15:13
12
11
10
9:4
3:0
Bit
Reserved
Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel
reference clock as on the platform and does not generate its own clock.
Link Training (LT) — RO. Default value is 0b.
0 = Link training completed.
1 = Link training is occurring.
Link Training Error (LTE ) — RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the given PCI
Express* link. The contents of this NLW field is undefined if the link has not successfully trained.
NOTE: 000001b = x1 link width, 0001000 = x4 link width (Enterprise applications only)
Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI Express*
link.
01h = Link is 2.5 Gb/s.
Port #
1
2
3
4
52–53h
See bit description
000001b, 000010b, 000100b
000001b
000001b
000001b
Possible Values
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
RO
16 bits
®
ICH6 uses the same