NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 117

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.5.1.1
5.5.1.2
Intel
Table 5-4. LPC Cycle Types Supported
Table 5-5. Start Field Bit Definitions
®
I/O Controller Hub 6 (ICH6) Family Datasheet
LPC Cycle Types
The ICH6 implements all of the cycle types described in the Low Pin Count Interface
Specification, Revision 1.0.
NOTES:
Start Field Definition
NOTE: All other encodings are RESERVED.
1. For memory cycles below 16 MB that do not target enabled firmware hub ranges, the ICH6 performs
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any
Encoding
Bits[3:0]
standard LPC memory cycles. It only attempts 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer,
it appears as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on
PCI, it appears as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it is
subsequently aborted, and the ICH6 returns a value of all 1s to the processor. This is done to maintain
compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
address. However, the 2-byte transfer must be word-aligned (i.e., with an address where A0=0). A DWord
transfer must be DWord-aligned (i.e., with an address where A1 and A0 are both 0).
Bus Master Read
Bus Master Write
0000
0010
0011
1111
Memory Read
Memory Write
Cycle Type
DMA Read
DMA Write
I/O Read
I/O Write
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a target.
Single: 1 byte only
Single: 1 byte only
1 byte only. Intel
transfers. See Note 1 below.
1 byte only. ICH6 breaks up 16- and 32-bit processor cycles into multiple 8-bit
transfers. See Note 1 below.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 2 below)
Can be 1, 2, or 4 bytes. (See Note 2 below)
Definition
Table 5-4
®
shows the cycle types supported by the ICH6.
ICH6 breaks up 16- and 32-bit processor cycles into multiple 8-bit
Comment
Functional Description
117