NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 522

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

UHCI Controllers Registers
13.2.5
522
FRBASEADD—Frame List Base Address Register
I/O Offset:
Default Value:
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD
loads this register prior to starting the schedule execution by the host controller. When written, only
the upper 20 bits are used. The lower 12 bits are written as 0’s (4-KB alignment). The contents of
this register are combined with the frame number counter to enable the host controller to step
through the Frame List in sequence. The two least significant bits are always 00. This requires
DWord-alignment for all list entries. This configuration supports 1024 Frame List entries.
31:12
11:0
Bit
Base Address — R/W. These bits correspond to memory address signals [31:12], respectively.
Reserved
Base + (08
Undefined
–
0Bh)
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
32 bits
R/W