NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 361
NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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10.1.27
10.2
Intel
Table 10-2. DMA Registers (Sheet 1 of 2)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
DMA I/O Registers (LPC I/F—D31:F0)
31:14
13:1
84h–86h
Bit
0
Port
0Ch
0Dh
0Ah
0Bh
0Eh
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
80h
81h
82h
83h
87h
88h
Base Address (BA) — R/W. This field provides the base address for the root complex register block
decode range. This address is aligned on a 16-KB boundary.
Reserved
Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed as the Root
Complex Register Block.
94h–96h
Alias
1Ch
1Dh
10h
12h
13h
14h
15h
16h
17h
18h
1Ah
1Bh
1Eh
1Fh
90h
91h
93h
97h
98h
11h
—
F0h
00000000h
Channel 0 DMA Base & Current Address
Channel 0 DMA Base & Current Count
Channel 1 DMA Base & Current Address
Channel 1 DMA Base & Current Count
Channel 2 DMA Base & Current Address
Channel 2 DMA Base & Current Count
Channel 3 DMA Base & Current Address
Channel 3 DMA Base & Current Count
Channel 0–3 DMA Command
Channel 0–3 DMA Status
Channel 0–3 DMA Write Single Mask
Channel 0–3 DMA Channel Mode
Channel 0–3 DMA Clear Byte Pointer
Channel 0–3 DMA Master Clear
Channel 0–3 DMA Clear Mask
Channel 0–3 DMA Write All Mask
Reserved Page
Channel 2 DMA Memory Low Page
Channel 3 DMA Memory Low Page
Channel 1 DMA Memory Low Page
Reserved Pages
Channel 0 DMA Memory Low Page
Reserved Page
Register Name
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
R/W
32 bit
000001XXb
000000XXb
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Default
0Fh
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
WO
WO
WO
RO
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