NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 744

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
744
Table 22-9. Clock Timings (Sheet 2 of 2)
NOTES:
1. CLK14 edge rates in a system as measured from 0.8 V to 2.0 V.
2. The CLK48 expects a 40/60% duty cycle.
3. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
4. The ICh6 can tolerate a maximum of 2 ns of jitter from the input BITCLK. Note that clock jitter may impact
5. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
f susclk
f ac97
fHDA
Sym
t26a
t27a
t28a
t26
t27
t28
t29
t30
t36
t37
t38
t39
t40
conditions.
system timing. If routing guidelines for AC ‘97 were not followed as published in the Platform Design Guides,
system designers should ensure the input clock jitter does not negatively impact the system timing.
SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN)
Operating Frequency
Input Jitter (refer to Clock Chip Specification)
High time
Low time
Rise time
Fall time
Operating Frequency
Frequency Tolerance
Input Jitter (refer to Clock Chip Specification)
High Time (Measured at 0.75Vcc)
Low Time (Measured at 0.35Vcc)
Period
Rise time
Fall time
Operating Frequency
High Time
Low Time
ACZ_BIT_CLK (Intel High Definition Audio Mode)
AC ’97 Clock (ACZ_BIT_CLK - AC ‘97 mode)
Parameter
Suspend Clock (SUSCLK)
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
18.75
18.75
9.997
Min
175
175
2.0
2.0
36
36
10
10
–
–
–
12.288
24.0
32
10.003
22.91
22.91
Max
100
300
700
700
6.0
6.0
45
45
–
–
2
Unit
MHz
MHz
ppm
ppm
kHz
ns
ns
ns
ns
us
us
ns
ns
ns
ns
ps
ps
Figure
22-1
22-1
22-1
22-1
22-1
22-1
Notes
4
5
5
6
6
6