NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 516

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

UHCI Controllers Registers
13.1.19
13.2
516
Table 13-2. USB I/O Registers
CWP—Core Well Policy Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub ports function
such that on read back they reflect the current state of the port, and not necessarily the state of the
last write to the register. This allows the software to poll the state of the port and wait until it is in
the proper state before proceeding. A host controller reset, global reset, or port reset will
immediately terminate a transfer on the affected ports and disable the port. This affects the
USBCMD register, bit 4 and the PORTSC registers, bits [12,6,2]. See individual bit descriptions
for more detail.
NOTES:
1. These registers are WORD writable only. Byte writes to these registers have unpredictable effects.
BASE +
0D–0Fh
08–0Bh
00–01h
02–03h
04–05h
06–07h
10–11h
12–13h
Offset
Bit
7:1
0Ch
0
Reserved
Static Bus Master Status Policy Enable (SBMSPE) — R/W.
0 = The UHCI host controller dynamically sets the Bus Master status bit (Power Management 1
1 = The UHCI host controller statically forces the Bus Master Status bit in power management
NOTE: The PCI Power Management registers are enabled in the PCI Device 31: Function 0 space
FRBASEADD
Status Register,[PMBASE+00h], bit 4) based on the memory accesses that are scheduled. The
default setting provides a more accurate indication of snoopable memory accesses in order to
help with software-invoked entry to C3 and C4 power states
space to 1 whenever the HCHalted bit (USB Status Register, Base+02h, bit 5) is cleared.
Mnemonic
PORTSC0
PORTSC1
USBINTR
SOFMOD
USBCMD
USBSTS
FRNUM
(PM_IO_EN), and can be moved to any I/O location (128-byte aligned).
—
C8h
00h
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Reserved
Port 0 Status/Control
Port 1 Status/Control
Register Name
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W
8 bits
Undefined
Default
0000h
0020h
0000h
0000h
0080h
0080h
40h
—
R/W (see Note 1)
R/WC, RO, R/W
R/WC, RO, R/W
(see Note 1)
(see Note 1)
R/WC
Type
R/W
R/W
R/W
R/W
—