NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 752

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
752
Table 22-16. SATA Interface Timings
Table 22-17. SMBus Timing
NOTES:
NOTE:
1. 20%
2. 80%
3. As measured from 100 mV differential crosspoints of last and first edges of burst.
4. Operating data period during Out-Of-Band burst transmissions.
1. t134 has a minimum timing for I
2. A device will timeout when any clock low exceeds this value.
3. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
4. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
Sym
t130
t131
t132
t133
t134
t135
t136
t137
t138
Sym
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
UI
Bus Tree Time Between Stop and Start Condition
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Device Time Out
Cumulative Clock Low Extend Time (slave device)
Cumulative Clock Low Extend Time (master device)
–
–
80% at transmitter
20% at transmitter
Operating Data Period
Rise Time
Fall Time
TX differential skew
COMRESET
COMWAKE transmit spacing
OOB Operating Data period
Parameter
Parameter
2
C of 0 ns, while the minimum timing for SMBus is 300 ns.
Intel
®
666.43
646.67
I/O Controller Hub 6 (ICH6) Family Datasheet
310.4
103.5
Min
0.2
0.2
–
Min
250
4.7
4.0
4.7
4.0
25
–
–
0
670.12
686.67
329.6
109.9
Max
0.41
0.41
20
Max
35
25
10
–
–
–
–
–
–
Units
ps
ps
ns
ns
ns
UI
UI
Units
ms
ms
ms
µs
µs
µs
µs
ns
ns
Figure
22-16
22-16
22-16
22-16
22-16
22-16
22-17
22-17
Fig
Notes
Notes
1
2
3
3
4
1
2
3
4