NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 345

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.1.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
0 = No action is taken when detecting a parity error.
1 = Enables the ICH6 LPC bridge to respond to parity errors detected on backbone interface.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
04
0007h
No
–
05h
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W, RO
16-bit
Core
345