NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 436

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.10.9
436
GP_LVL2—GPIO Level for Input or Output 2 Register[63:32]
Offset Address:
Default Value:
Lockable:
31:18
17:16
15:10
Bit
9:8
7:3
2:0
Reserved. Read-only 0
GP_LVL[49:48] — R/W. The corresponding GP_LVL[n] bit can be updated by software to drive a
high or low value on the output pin. Since these bits correspond to GPIO that are in the processor I/
O and core well, respectively, these bits will be reset by PLTRST#.
0 = low
1 = high
Reserved. Read-only 0
GP_LVL[41:40] — R/W. The corresponding GP_LVL[n] bit reflects the state of the input signal.
Writes will have no effect. Since these bits correspond to GPIO that are in the core well, these bits
will be reset by PLTRST#.
0 = low
1 = high
Reserved. Read-only 0
GP_LVL[34:32] — R/W. If GPIOn is programmed to be an output (via the corresponding bit in the
GP_IO_SEL register), then the corresponding GP_LVL[n] bit can be updated by software to drive a
high or low value on the output pin. If GPIOn is programmed as an input, then the corresponding
GP_LVL bit reflects the state of the input signal (1 = high, 0 = low). Writes will have no effect.
0 = low
1 = high
Since these bits correspond to GPIO that are in the core well, these bits will be reset by PLTRST#.
GPIOBASE +38h
00030207h
No
§
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
R/W
32-bit
See below