NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 670

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.2.35
18.2.36
670
®
High Definition Audio Controller Registers (D27:F0)
SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel
Memory Address: Input Stream[0]: HDBAR + 84h
Default Value:
SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel
Memory Address: Input Stream[0]: HDBAR + 88h
Default Value:
31:0
31:0
Bit
Bit
®
Link Position in Buffer — RO. Indicates the number of bytes that have been received off the link.
This register will count from 0 to the value in the Cyclic Buffer Length register and then wrap to 0.
Cyclic Buffer Length — R/W. Indicates the number of bytes in the complete cyclic buffer. This
register represents an integer number of samples. Link Position in Buffer will be reset when it
reaches this value.
Software may only write to this register after Global Reset, Controller Reset, or Stream Reset has
occurred. This value should be only modified when the RUN bit is 0. Once the RUN bit has been set
to enable the engine, software must not write to this register until after the next reset is asserted, or
transfer may be corrupted.
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + A4h
Input Stream[2]: HDBAR + C4h
Input Stream[3]: HDBAR + E4h
Output Stream[0]: HDBAR + 104h
Output Stream[1]: HDBAR + 124h
Output Stream[2]: HDBAR + 144h
Output Stream[3]: HDBAR + 164h
00000000h
Input Stream[1]: HDBAR + A8h
Input Stream[2]: HDBAR + C8h
Input Stream[3]: HDBAR + E8h
Output Stream[0]: HDBAR + 108h
Output Stream[1]: HDBAR + 128h
Output Stream[2]: HDBAR + 148h
Output Stream[3]: HDBAR + 168h
00000000h
®
High Definition Audio Controller—D27:F0)
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Size:
Attribute:R/W
Attribute:RO
Size:
32 bits
32 bits