NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 515

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

13.1.18
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
Bit
7:2
Bit
1
0
7
6
5
4
3
2
1
0
Reserved
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI at the end of a
pass-through. This can occur if an SMI is generated in the middle of a pass-through, and needs to
be serviced later.
0 = Disable
1 = Enable
Pass Through State (PSTATE) — RO.
0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
A20Gate Pass-Through Enable (A20PASSEN) — R/W.
0 = Disable.
1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence
SMI on USB IRQ Enable (USBSMIEN) — R/W.
0 = Disable
1 = Enable. USB interrupt will cause an SMI event.
SMI on Port 64 Writes Enable (64WEN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 11 will cause an SMI event.
SMI on Port 64 Reads Enable (64REN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 10 will cause an SMI event.
SMI on Port 60 Writes Enable (60WEN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 9 will cause an SMI event.
SMI on Port 60 Reads Enable (60REN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 8 will cause an SMI event.
involving writes to port 60h and 64h does not result in the setting of the SMI status bits.
C4h
00h
Description
Description
Attribute:
Size:
UHCI Controllers Registers
R/W
8 bits
515