NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 381

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.5.3
10.5.4
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one
Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8.
DAT—Data Register (LPC I/F—D31:F0)
Memory Address
Default Value:
This is a 32-bit register specifying the data to be read or written to the register pointed to by the
Index register. This register can only be accessed in DWord quantities.
EOIR—EOI Register (LPC I/F—D31:F0)
Memory Address
Default Value:
The EOI register is present to provide a mechanism to maintain the level triggered semantics for
level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this
register, and compare it with the vector field for each entry in the I/O Redirection Table. When a
match is found, the Remote_IRR bit (Index Offset 10h, bit 14) for that I/O Redirection Entry will
be cleared.
interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which
was prematurely reset will not be lost because if its input remained active when the Remote_IRR
bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are
actually used. Bits 31:8 are ignored by the ICH6.
31:8
Bit
7:0
Bit
7:0
APIC Data — R/W. This is a 32-bit register for the data to be read or written to the APIC indirect
register
Reserved. To provide for future expansion, the processor should always write a value of 0 to
Bits 31:8.
Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this
field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match
is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
(Figure
FEC0_0010h
00000000h
FEC0_0040h
N/A
10-5) pointed to by the Index register (Memory Address FEC0_0000h).
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
WO
32 bits
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