NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 378

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NH82801FBM S L89K

Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FBM S L89K

Lead Free Status / RoHS Status
Compliant
LPC Interface Bridge Registers (D31:F0)
10.4.10
378
ELCR1—Master Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat
timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Bit
2:0
7
6
5
4
3
IRQ7 ECL — R/W.
0 = Edge.
1 = Level.
IRQ6 ECL — R/W.
0 = Edge.
1 = Level.
IRQ5 ECL — R/W.
0 = Edge.
1 = Level.
IRQ4 ECL — R/W.
0 = Edge.
1 = Level.
IRQ3 ECL — R/W.
0 = Edge.
1 = Level.
Reserved. Must be 0.
4D0h
00h
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W
8 bits

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