NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 410

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.8.3.6
10.8.3.7
10.8.3.8
410
LV2 — Level 2 Register
I/O Address:
Default Value:
Lockable:
Power Well:
NOTE: This register should not be used by Intel iA64 processors or systems with more than 1 logical processor,
LV3—Level 3 Register (Mobile Only)
I/O Address:
Default Value:
Lockable:
NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a LVL3
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical processor,
LV4—Level 4 Register (Mobile Only)
I/O Address:
Default Value:
Lockable:
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical processor,
Bit
7:0
Bit
7:0
Bit
7:0
unless appropriate semaphoring software has been put in place to ensure that all threads/processors
are ready for the C2 state when the read to this register occurs
transition. In the event that software attempts to simultaneously read the LVL2 and LVL3 registers
(which is illegal), the ICH6 will ignore the LVL3 read, and only perform a C2 transition.
unless appropriate semaphoring software has been put in place to ensure that all threads/processors
are ready for the C3 state when the read to this register occurs.
unless appropriate semaphoring software has been put in place to ensure that all threads/processors
are ready for the C4 state when the read to this register occurs.
Reads to this register return all 0s, writes to this register have no effect. Reads to this register
generate a “enter a C3 power state” to the clock control logic. The C3 state persists until a break
event occurs.
Reads to this register return all 0s, writes to this register have no effect. Reads to this register
generate a “enter a C4 power state” to the clock control logic. The C4 state persists until a break
event occurs.
Reads to this register return all 0s, writes to this register have no effect. Reads to this register
generate a “enter a level 2 power state” (C2) to the clock control logic. This will cause the STPCLK#
signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or
FORCE_THTL) will be ignored.
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
PMBASE + 15h (ACPI P_BLK + 5)
00h
No
PMBASE + 16h (ACPI P_BLK + 6)
00h
No
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
Power Well:
Attribute:
Size:
Usage:
Power Well:
RO
RO
RO
8-bit
ACPI or Legacy
8-bit
ACPI or Legacy
Core
8-bit
ACPI or Legacy
Core