NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 148

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.13.1.3
148
Table 5-21. INIT# Going Active
Figure 5-6. Coprocessor Error Timing Diagram
FERR#/IGNNE# (Numeric Coprocessor Error /
Ignore Numeric Error)
The ICH6 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is
enabled via the COPROC_ERR_EN bit (Chipset Configuration Registers:Offset 31FFh:bit 1).
FERR# is tied directly to the Coprocessor Error signal of the processor. If FERR# is driven active
by the processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR
register (I/O Register F0h), the ICH6 negates the internal IRQ13 and drives IGNNE# active.
IGNNE# remains active until FERR# is driven inactive. IGNNE# is never driven active unless
FERR# is active.
If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal IRQ13, nor
will the write to F0h generate IGNNE#.
Shutdown special cycle from processor.
PORT92 write, where INIT_NOW (bit 0)
transitions from a 0 to a 1.
PORTCF9 write, where SYS_RST (bit 1) was a 0
and RST_CPU (bit 2) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected
to be driven by the external microcontroller
(KBC).
Processor BIST
I/O Write to F0h
Internal IRQ13
Cause of INIT# Going Active
IGNNE#
FERR#
Intel
0 to 1 transition on RCIN# must occur before the Intel
ICH6 will arm INIT# to be generated again.
NOTE: RCIN# signal is expected to be high during
To enter BIST, software sets CPU_BIST_EN bit and then
does a full processor reset using the CF9 register.
®
I/O Controller Hub 6 (ICH6) Family Datasheet
S3
states. Transition on the RCIN# signal in those
states (or the transition to those states) may not
necessarily cause the INIT# signal to be
generated to the processor.
HOT
and low during S3
Comment
COLD
, S4, and S5
®